• Phase margin with various resistor configurations - confirm via math and simulation that there are no excessive oscillations on Vin
• Frequency response and stability were simulated in LTspice and briefly investigated mathematically using the Desmos file here (note that both use a buck converter with a 0.6V FB pin reference as opposed to 0.8V for ours, but the idea is the same). My first thought was that large resistor values would be ideal to minimize power loss, but it was observed in simulation that too high of resistor values for the diff amplifier would result in large oscillations (possibly due to decreased phase margin) so the resistor values were kept fairly standard. I also tested adding extra capacitors to increase the phase margin, they didn’t seem to have too much effect especially since the op amp is acting as an attenuator overall, so there isn’t really a unity gain frequency. That being said I plan to DNP the capacitors on the next board so we can try adding some on if need be.
• I also tried the simulation with several different op amps to make sure there wasn’t a specific op amp parameter I had missed that would cause instability if a slightly different one was used - remained stable for various combinations.
• I am changing the feedback potentiometer from 10k to 1k - this made it easier to balance the resistor values to get a stable input voltage with low ripple in simulation (~10mV).

While I honestly don’t fully understand the mechanics of why certain resistor value combinations suddenly caused large oscillations in Vin, my understanding is that it’s due in some part to changing RC time constants for the various feedback loops, causing one of the controlled voltages (FB, Vin) to overshoot (basically becoming an underdamped oscillator) causing the next voltage to follow suit, etc. I have tried in vain to figure it out more than that, might be interesting to revisit with some proper 3rd year control systems knowledge.

https://docs.google.com/spreadsheets/d/1apIF_unxfYD7fnaug3Fj4Ni4ORDPF8y0npDXhlCV8p0/edit?gid=0#gid=0

I was originally using the LTC8648S for simulation but at this point I replaced it with the LTC3404 which better emulates our actual buck converter (same FB reference voltage, both current-mode control, similar pin functions).

I also made the simulated solar cell network match the current solar panel design of 5S 12P with semi-accurate cell parameters according to the datasheet.

After tuning the various resistors to keep the slew rate high while minimizing overshoot/undershoot, the combination shown here produced acceptable simulation results: max 45mV overshoot on a full sweep from 10V to 13.1V.