I2C is a synchronous, serial communication bus which facilitates communication between a controller (or multiple controllers) and a single or multiple peripheral devices, using only 2 wires (SDA and SCL).
Figure 1: Typical example I2C Bus
Data rates for I2C fall between asynchronous serial (like UART) and SPI; most I2C devices can communicate at 100kHz or 400kHz.
At a hardware level, each I2C bus consists of two signals, the clock signal (SCL) and the data signal (SDA). The clock signal is ALWAYS generated by the current bus controller, though some peripherals may force the clock low at times to delay the controller sending more data (aka clock stretching).
I2C bus drivers are "open drain", meaning they can pull the corresponding signal line low, but cannot drive it high (thus no bus contention where one device is trying to drive the line high, while another drives low → causing a short). Each signal has a pull-up resistor on it to restore the signal to high when no device is asserting it low as shown in Figure 1. Note, sometimes boards have internal pull-up resistors for this already.
An I2C message is broken up into two types of frame: an ADDRESS frame, where the controller indicates the peripheral to which the message is being sent, and one or more DATA frames, which are 8-bit data messages passed from controller to peripheral or vice-versa.
- Start Condition: To initiate the address frame, the controller device leaves the SCL high and pulls SDA low. This puts all the peripheral devices on notice that a transmission is about to start. If two controllers wish to take ownership of the bus at one time, whichever device pulls SDA low first wins the race and gains control of the bus
- Address Frame: Address frame is always the first in any new sequence. For a 7-bit address, the address is clocked out most significant bit (MSB) first, followed by a R/W bit indicating whether this is a read (1) or write (0) operation. The 9th bit of the frame is the NACK/ACK bit. This is the case for all frames. Once the first 8 bits of the frame are sent, the receiving device is given control over SDA. If the receiving device does not pull the SDA line low before the 9th clock pulse, it can be inferred that the receiving device either did not receive the data or did not know how to parse the message. In this case, the exchange halts and its up to the controller of the system to decide how to proceed
- Data Frames: After the address frame has been sent, data can begin being transmitted. The controller will simply continue generating clock pulses at a regular interval, and the data will be placed on SDA by either the controller or the peripheral, depending on whether the R/W bit indicated a read or write operation. The number of data frames is arbitrary, and most peripheral devices will auto-increment the internal register, meaning that subsequent reads or writes will come from the next register in line.
- Stop Condition: Once all the data frames have been sent, the controller will generate a stop condition. Stop conditions are defined by a 0→1 (low to high) transition on SDA after a 0→1 transition on SCL, with SCL remaining high. During normal data writing operation, the value on SDA should NOT change when SCL is high to avoid false stop conditions.
I2C Message Breakdown